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data sheet ics8536ag-02 revision a july 21, 2010 1 ?2010 integrated device technology, inc. low skew, 1-to-6, dual crystal/lvcmos-to- 3.3v, 2.5v lvpecl fanout buffer ics8536-02 general description the ics8536-02 is a low skew, high performance 1-to-6, dual crystal or lvcmos input-to-3.3v, 2.5v lvpecl fanout buffer. the ics8536-02 has selectable crystal or single ended clock input. the single ended clock input accepts lvcmos or lvttl input levels and translates them to lvpecl levels. the output enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. guaranteed output and part-to-part skew characteristics make the ics8536-02 ideal for those applications demanding well defined performance and repeatability. features ? six 3.3v, 2.5v differential lvpecl output pairs ? selectable crystal oscillator interface or lvcmos/lvttl single-ended input ? maximum output frequency: 266mhz ? crystal frequency range: 14mhz ? 40mhz ? output skew: 55ps (maximum) ? part-to-part skew: 500ps (maximum) ? propagation delay: 1.85ns (maximum), 3.3v ? additive phase jitter, rms: 0.149ps (typical) ? full 3.3v or 2.5v supply modes ? 0c to 70c ambient operating temperature ? industrial temperature information available upon request ? available in both standard (rohs 5) and lead-free (rohs 6) packages pin assignment ics8536-02 24-lead tssop 4.4mm x 7.8mm x 0.925mm package body g package top view block diagram 00 01 1x osc osc d le q q0 nq0 q5 nq5 6 lvpecl outputs pullup pulldown pulldown pulldown clk_en clk_sel0 clk_sel1 xtal_in0 xtal_out0 xtal_in1 xtal_out1 clk0 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 nq2 q2 v cc nq1 q1 v ee nq0 q0 clk_sel0 xtal_in0 xtal_out0 clk_en q3 nq3 q4 v cc v cc nq4 q5 nq5 clk_sel1 xtal_out1 xtal_in1 clk 0
ics8536ag-02 revision a july 21, 2010 2 ?2010 integrated device technology, inc. ics8536-02 data sheet 1-to-6, dualcrystal/l vcmos-to-3.3v, 2.5v lvpecl fanout buffer table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1, 2 nq2, q2 output differential out put pair. lvpecl in terface levels. 3, 19, 22 v cc power power supply pins. 4, 5 nq1, q1 output differential out put pair. lvpecl in terface levels. 6v ee power negative supply pin. 7, 8 nq0, q0 output differential out put pair. lvpecl in terface levels. 9, 16 clk_sel0, clk_sel1 input pulldown clock select pins. lvcmos/l vttl interface levels. see table 3b. 10, 11 xtal_in0, xtal_out0 input parallel resonant crystal interface. xtal_out0 is the output, xtal_in0 is the input. 12 clk_en input pullup synchronizing clock enable. when high, clock outputs follow clock input. when low, the outputs are disabled. lvcmos / lvttl interface levels. see table 3a. 13 clk0 input pulldown single-ended clock input. lvcmos/lvttl interface levels. 14, 15 xtal_in1, xtal_out1 input parallel resonant crystal interface. xtal_out1 is the output, xtal_in1 is the input. 17, 18 nq5, q5 output differential out put pair. lvpecl in terface levels. 20, 21 nq4, q4 output differential out put pair. lvpecl in terface levels. 23, 24 nq3, q3 output differential out put pair. lvpecl in terface levels. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 4pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ?
ics8536ag-02 revision a july 21, 2010 3 ?2010 integrated device technology, inc. ics8536-02 data sheet 1-to-6, dualcrystal/l vcmos-to-3.3v, 2.5v lvpecl fanout buffer function tables table 3. control input function table after clk_en switches, the clock outputs are disabled or enabl ed following a rising and falling input clock edge as show in fig ure 1. in the active mode, the state of the outputs are a function of the selected clock input. figure 1. clk_en timing diagram inputs outputs clk_en clk_sel1 clk_sel0 selec ted source q[0:5] nq[0:5] 0 0 0 xtal0 disabled disabled 0 0 1 xtal1 disabled disabled 0 1 x clk0 disabled disabled 1 0 0 xtal0 enabled enabled 1 0 1 xtal1 enabled enabled 1 1 x clk0 enabled enabled enabled disabled clk0, xtal0, xtal1 clk_en nq[0:5] q[0:5]
ics8536ag-02 revision a july 21, 2010 4 ?2010 integrated device technology, inc. ics8536-02 data sheet 1-to-6, dualcrystal/l vcmos-to-3.3v, 2.5v lvpecl fanout buffer absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v cc = 3.3v 5%, v ee = 0v, t a = 0c to 70c table 4b. power supply dc characteristics, v cc = 2.5v 5%, v ee = 0v, t a = 0c to 70c table 4c. lvcmos/lvttl dc characteristics, t a = 0c to 70c item rating supply voltage, v cc 4.6v inputs, v i xtal_in other input 0v to v cc -0.5v to v cc + 0.5v outputs, i o (lvpecl) continuous current surge current 50ma 100ma package thermal impedance, ja 87.8 c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditio ns minimum typical maximum units v cc core supply voltage 3.135 3.3 3.465 v i ee power supply current 89 ma symbol parameter test conditions minimum typical maximum units v cc core supply voltage 2.375 2.5 2.625 v i ee power supply current 84 ma symbol parameter test conditions minimum typical maximum units v ih input high voltage v cc = 3.3v 2 v cc + 0.3 v v cc = 2.5v 1.7 v cc + 0.3 v v il input low voltage v cc = 3.3v -0.3 0.8 v v cc = 2.5v -0.3 0.7 v i ih input high current clk0, clk_sel[0:1] v cc = v in = 3.465v or 2.625v 150 a clk_en v cc = v in = 3.465v or 2.625v 5 a i il input low current clk0, clk_sel[0:1] v cc = 3.465v or 2.625v, v in = 0v -5 a clk_en v cc = 3.465v or 2.625v, v in = 0v -150 a
ics8536ag-02 revision a july 21, 2010 5 ?2010 integrated device technology, inc. ics8536-02 data sheet 1-to-6, dualcrystal/l vcmos-to-3.3v, 2.5v lvpecl fanout buffer table 4d. lvpecl dc characteristics, v cc = 3.3v 5%, v ee = 0v, t a = 0c to 70c note 1: outputs terminated with 50 ? to v cc ? 2v. table 4e. lvpecl dc characteristics, v cc = 2.5v 5%, v ee = 0v, t a = 0c to 70c note 1: outputs terminated with 50 ? to v cc ? 2v. table 5. crystal characteristics note: characterized using an 18pf parallel resonant crystal. symbol parameter test conditio ns minimum typical maximum units v oh output high voltage; note 1 v c c ? 1.4 v cc ? 0.9 v v ol output low voltage; note 1 v cc ? 2.0 v cc ? 1.7 v v swing peak-to-peak output voltage swing 0.6 1.0 v symbol parameter test conditio ns minimum typical maximum units v oh output high voltage; note 1 v cc ? 1.4 v cc ? 0.9 v v ol output low voltage; note 1 v cc ? 2.0 v cc ? 1.5 v v swing peak-to-peak output voltage swing 0.4 1.0 v parameter test conditions mi nimum typical maximum units mode of oscillation fundamental frequency 14 40 mhz equivalent series resistance (esr) 50 ? shunt capacitance 7pf
ics8536ag-02 revision a july 21, 2010 6 ?2010 integrated device technology, inc. ics8536-02 data sheet 1-to-6, dualcrystal/l vcmos-to-3.3v, 2.5v lvpecl fanout buffer ac electrical characteristics table 6a. ac characteristics, v cc = 3.3v 5%, v ee = 0v, t a = 0c to 70c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note: all parameters measured at f out unless noted otherwise. note 1: measured from v cc /2 of the input crossing point to the differential output crossing point. note 2: driving clk0 input. note 3: defined as skew between outputs at the same supply volt age and with equal load conditions. measured at the output diffe rential cross points. note 4: this parameter is defined in accordance with jedec standard 65. note 5: defined as skew between outputs on different devices o perating at the same supply voltage , same temperature, same frequ ency and with equal load conditions. using the same type of inputs on each device, the outputs are measured at the differential cross po ints. note 6: measured on either xtal0 or xtal1 when sing le-ended clk0 switching at 150mhz or 250mhz. table 6b. ac characteristics, v cc = 2.5v 5%, v ee = 0v, t a = 0c to 70c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note: all parameters measured at f out unless noted otherwise. note 1: measured from v cc /2 of the input crossing point to the differential output crossing point. note 2: driving clk0 input. note 3: defined as skew between outputs at the same supply volt age and with equal load conditions. measured at the output diffe rential cross points. note 4: this parameter is defined in accordance with jedec standard 65. note 5: defined as skew between outputs on different devices o perating at the same supply voltage , same temperature, same frequ ency and with equal load conditions. using the same type of inputs on each device, the outputs are measured at the differential cross po ints. note 6: measured on either xtal0 or xtal1 when sing le-ended clk0 switching at 150mhz or 250mhz. symbol parameter test conditio ns minimum typical maximum units f out output frequency 266 mhz t pd propagation delay; note 1 1.35 1.85 ns t jit buffer additive phase jitter, rms; note 2 155.52mhz, integration range: 12khz ? 20mhz 0.149 ps t sk(o) output skew; note 3, 4 55 ps t sk(pp) part-to-part skew; note 4, 5 500 ps t r / t f output rise/fall time 20% to 80% 200 700 ps odc output duty cycle 47 53 % mux_ isolation mux isolation; note 6 ? = 150mhz 48 db ? = 250mhz 45 db symbol parameter test conditio ns minimum typical maximum units f out output frequency 266 mhz t pd propagation delay; note 1 1.4 1.9 ns t jit buffer additive phase jitter, rms; note 2 155.52mhz, integration range: 12khz ? 20mhz 0.149 ps t sk(o) output skew; note 3, 4 55 ps t sk(pp) part-to-part skew; note 4, 5 500 ps t r / t f output rise/fall time 20% to 80% 200 700 ps odc output duty cycle 47 53 % mux_ isolation mux isolation; note 6 ? = 150mhz 40 db ? = 250mhz 40 db
ics8536ag-02 revision a july 21, 2010 7 ?2010 integrated device technology, inc. ics8536-02 data sheet 1-to-6, dualcrystal/l vcmos-to-3.3v, 2.5v lvpecl fanout buffer additive phase jitter the spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the spec ified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the require d offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offset from the fundamen tal. by investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher t han the noise floor of the device. this is illustrated above. the device meets the noise floor of what is shown, but can actually be lower. the phase noise is dependent on the input source and measurement equipment. the source generator "sma 100 generator 9khz ? 6ghz as external input to an agilent 8133a 3hgz pulse generator?. ssb phase noise dbc/hz offset from carrier frequency (hz) 155.52mhz rms phase jitter (random) 12khz to 20mhz = 0.149ps (typical)
ics8536ag-02 revision a july 21, 2010 8 ?2010 integrated device technology, inc. ics8536-02 data sheet 1-to-6, dualcrystal/l vcmos-to-3.3v, 2.5v lvpecl fanout buffer parameter measureme nt information 3.3v lvpecl output load ac test circuit part-to-part skew propagation delay 2.5v lvpecl output load ac test circuit output skew output duty cycle/pulse width/period scope qx nqx lvpecl v ee v cc 2v -1.3v 0.165v t sk(pp) part 1 part 2 nqx qx nqy qy nq[0:5] q[0:5] t pd v cc 2 clk0 scope qx nqx lvpecl v ee -0.5v 0.125v v cc 2v t sk(o) nqx qx nqy qy nq[0:5] q[0:5] t pw t period t pw t period odc = x 100%
ics8536ag-02 revision a july 21, 2010 9 ?2010 integrated device technology, inc. ics8536-02 data sheet 1-to-6, dualcrystal/l vcmos-to-3.3v, 2.5v lvpecl fanout buffer parameter measurement in formation, continued output rise/fall time mux_isolation application information recommendations for unused input and output pins inputs: crystal inputs for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from xtal_in to ground. clk0 input for applications not requiring the use of the clock input, it can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from the clk0 input to ground. lvcmos control pins all control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvpecl outputs the unused lvpecl output pair c an be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. 20% 80% 80% 20% t r t f v swing nq[0:5] q[0:5] amplitude (db) a0 spectrum of output signal q mux _isol = a0 ? a1 (fundamental) frequency ? mux selects static input mux selects active input clock signal a1
ics8536ag-02 revision a july 21, 2010 10 ?2010 integrated device technology, inc. ics8536-02 data sheet 1-to-6, dualcrystal/l vcmos-to-3.3v, 2.5v lvpecl fanout buffer crystal input interface the ics8536-02 has been characterized with 18pf parallel resonant crystals. the capacitor values shown in figure 2 below were determined using an 18pf parallel resonant crystal and were chosen to minimize the ppm error. figure 2. crystal input interface overdriving the xtal interface the xtal_in input can accept a single-ended lvcmos signal through an ac coupling capacitor. a general interface diagram is shown in figure 3a. the xtal_out pin can be left floating. the maximum amplitude of the input signal should not exceed 2v and the input edge rate can be as slow as 10ns. this configuration requires that the output impedanc e of the driver (ro) plus the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and making r2 50 ? . by overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal. figure 3a. general diagram for lvcmos driver to xtal input interface figure 3b. general diagram for lvpecl driver to xtal input interface xtal_in xtal_out x1 18pf parallel crystal c1 33pf c2 27pf r2 100 r1 100 rs 43 ro ~ 7 ohm driv er_lvcmos zo = 50 ohm c1 0.1uf 3.3v 3.3v cry stal input interf ace xta l _ i n xta l _ o u t cry stal input interf ace xtal_in xtal_out r3 50 c1 0.1uf r2 50 r1 50 zo = 50 ohm lvpecl zo = 50 ohm vcc=3.3v
ics8536ag-02 revision a july 21, 2010 11 ?2010 integrated device technology, inc. ics8536-02 data sheet 1-to-6, dualcrystal/l vcmos-to-3.3v, 2.5v lvpecl fanout buffer termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. the differential outputs are lo w impedance follower outputs that generate ecl/lvpecl compatible out puts. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 4a and 4b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 4a. 3.3v lvpecl output termination figure 4b. 3.3v lvpecl output termination 3.3v v cc - 2v r1 50 ? r2 50 ? rtt z o = 50 ? z o = 50 ? + _ rtt = * z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v lvpecl input r1 84 ? r2 84 ? 3.3v r3 125 ? r4 125 ? z o = 50 ? z o = 50 ? lvpecl input 3.3v 3.3v + _
ics8536ag-02 revision a july 21, 2010 12 ?2010 integrated device technology, inc. ics8536-02 data sheet 1-to-6, dualcrystal/l vcmos-to-3.3v, 2.5v lvpecl fanout buffer termination for 2.5v lvpecl outputs figure 5a and figure 5b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to v cc ? 2v. for v cc = 2.5v, the v cc ? 2v is very close to ground level. the r3 in figure 5b can be eliminated and the termination is shown in figure 5c. figure 5a. 2.5v lvpecl driver termination example figure 5c. 2.5v lvpecl driver termination example figure 5b. 2.5v lvpecl driver termination example 2.5v lvpecl driver v cco = 2.5v 2.5v 2.5v 50 ? 50 ? r1 250 r3 250 r2 62.5 r4 62.5 + ? 2.5v lvpecl driver v cco = 2.5v 2.5v 50 ? 50 ? r1 50 r2 50 + ? 2.5v lvpecl driver v cco = 2.5v 2.5v 50 ? 50 ? r1 50 r2 50 r3 18 + ?
ics8536ag-02 revision a july 21, 2010 13 ?2010 integrated device technology, inc. ics8536-02 data sheet 1-to-6, dualcrystal/l vcmos-to-3.3v, 2.5v lvpecl fanout buffer power considerations this section provides information on power dissipa tion and junction temperature for the ics8536-02. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics8536-02 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. power (core) max = v cc_max * i ee_max = 3.465v * 89ma = 308.385mw power (outputs) max = 30mw/loaded output pair if all outputs are loaded, the total power is 6 * 30mw = 180mw total power_ max (3.3v, with all outputs switching) = 308.385mw + 180mw = 488.385mw 2. junction temperature. junction temperature, tj, is the temperat ure at the junction of the bond wire and bond pad, and directly affects the reliabilit y of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 87.8c/w per table 7 below. therefore, tj for an ambient temperature of 70c with all outputs switching is: 70c + 0.488w * 87.8c/w = 112.8c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 7. thermal resitance ja for 24 lead tssop, forced convection ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 87.8c/w 83.5c/w 81.3c/w
ics8536ag-02 revision a july 21, 2010 14 ?2010 integrated device technology, inc. ics8536-02 data sheet 1-to-6, dualcrystal/l vcmos-to-3.3v, 2.5v lvpecl fanout buffer 3. calculations and equations. the purpose of this section is to calculate the power dissipation fo r the lvpecl output pair. lvpecl output driver circuit and termination are shown in figure 6. figure 6. lvpecl driver circuit and termination t o calculate worst case power dissipation into the load, use the following equations which assume a 50 ? load, and a termination voltage of v cc ? 2v. for logic high, v out = v oh_max = v cc_max ? 0.9v (v cc_max ? v oh_max ) = 0.9v for logic low, v out = v ol_max = v cc_max ? 1.7v (v cc_max ? v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v oh_max ) = [(2v ? (v cc_max ? v oh_max ))/r l ] * (v cc_max ? v oh_max ) = [(2v ? 0.9v)/50 ? ] * 0.9v = 19.8mw pd_l = [(v ol_max (v cc_max ? 2v))/r l ] * (v cc_max ? v ol_max ) = [(2v ? (v cc_max ? v ol_max ))/r l ] * (v cc_max ? v ol_max ) = [(2v ? 1.7v)/50 ? ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw v out v cc v cc - 2v q1 rl 50
ics8536ag-02 revision a july 21, 2010 15 ?2010 integrated device technology, inc. ics8536-02 data sheet 1-to-6, dualcrystal/l vcmos-to-3.3v, 2.5v lvpecl fanout buffer reliability information table 8. ja vs. air flow table for a 24 lead tssop transistor count the transistor count for ics8536-02 is: 467 package outline and package dimensions package outline - g suffix for 24 lead tssop table 9. package dimensions reference document: jedec publication 95, mo-153 ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 87.8c/w 83.5c/w 81.3c/w all dimensions in millimeters symbol minimum maximum n 24 a 1.20 a1 0.5 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 7.70 7.90 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 0 8 aaa 0.10
ics8536ag-02 revision a july 21, 2010 16 ?2010 integrated device technology, inc. ics8536-02 data sheet 1-to-6, dualcrystal/l vcmos-to-3.3v, 2.5v lvpecl fanout buffer ordering information table 10. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 8536ag-02 ics8536ag-02 24 lead tssop tube 0c to 70c 8536ag-02t ics8536ag-02 24 lead tssop 2500 tape & reel 0c to 70c 8536AG-02LF ics8536ag-02l ?lead-free? 24 lead tssop tube 0c to 70c 8536AG-02LFt ics8536ag-02l ?lead-free? 24 lead tssop 2500 tape & reel 0c to 70c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, whic h would result from its use. no other circuits, patents, or l icenses are implied. this produc t is intended for use in normal commercial applications. any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves t he right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments.
ics8536-02 data sheet 1-to-6, dualcrystal/l vcmos-to-3.3v, 2.5v lvpecl fanout buffer disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ri sk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2010. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution

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